1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a charge storing means (for example, a floating gate in a floating gate (FG) type, a charge trap in a nitride film in a metal-oxide-nitride-oxide-semiconductor (MONOS) type and metal-nitride-oxide-semiconductor (MNOS) type, a charge trap near the interface between a top insulating film and a nitride film, or fine particle conductor, etc.) inside a gate insulating film between a channel-forming region and a gate electrode of a memory transistor and performing as basic operations the electrical injection of charges (electrons or holes) in the charge storing means for storing or withdrawing of the same from the same and a method of reading the same.
2. Description of the Related Art
Non-volatile semiconductor memories include, for example, the FG type wherein charge storing means (floating gate) for holding charges is made planarly and, also, the MONOS type wherein charge storing means (charge traps) are made planarly dispersed.
In an FG type non-volatile memory transistor, a floating gate comprised of polycrystalline silicon etc. is stacked on a channel-forming region of a semiconductor via a gate insulating film. A control gate is further stacked on the floating gate via an inter-gate insulating film comprised of an oxide-nitride-oxide (ONO) film etc.
On the other hand, in a MONOS type non-volatile memory transistor, a tunnel insulating film comprised for example of a silicon oxide film, an oxynitride film, etc., an interlayer insulating film comprised of a nitride film, an oxynitride film, etc., and a top insulating film comprised of a silicon oxide film are successively stacked on the channel-forming region of the semiconductor. A gate electrode is formed on the top insulating film.
In a MONOS type non-volatile semiconductor memory, carrier traps serving mainly for holding charges in the nitride film (Si.sub.x N.sub.y (0&lt;x&lt;1, 0&lt;y&lt;1)) or at an interface between the top insulating film and the nitride film are discretely dispersed spatially (that is, in the planar direction and film thickness direction), so the charge holding characteristic depends on the energy and spatial distribution of the charge captured by the carrier trap in the Si.sub.x N.sub.y film in addition to the tunnel insulating film thickness.
When a leakage current path locally occurs in the tunnel insulating film, in the FG type, much of the charge passes through the leakage path and the charge holding characteristic is liable to decline, while in the MONOS type, since the charge storing means are spatially dispersed, the local charges around the leakage path pass through the leakage path and only locally leaks and therefore the charge holding characteristic of the overall memory device is resistant to decline.
Therefore, in the MONOS type, the problem of the decline of the charge holding characteristic caused by a tunnel insulating film becoming thinner is not as serious as in the FG type. Accordingly, the MONOS type is superior to the FG type in scaling of the tunnel oxide film in a fine memory transistor having an extremely short gate length.
In the above FG type non-volatile memory or MONOS type or other non-volatile memory where the charge storing means of the memory transistors are planarly dispersed, to reduce the cost per bit, increase the integration, and realize a large scale non-volatile memory, it is essential to realize a one-transistor type cell structure.
However, particularly in a MONOS type or other non-volatile memory, the mainstream is a two-transistor type wherein a selection transistor is connected to a memory transistor. Various studies are currently underway for establishing the one-transistor cell technique.
To establish the one-transistor cell technique, improvement of the disturb characteristic is necessary in addition to optimization of the element structure such as the gate insulating film including the charge storing means and improvement of the reliability. As one means for improving the disturb characteristic of a MONOS type non-volatile memory, studies are being conducted to set the tunnel insulating film thicker than the normal film thickness of 1.6 nm to 2.0 nm.
In a one-transistor cell, since there is no selection transistor in the cell, it is important to reduce the disturb characteristic of the memory transistor in non-selected cells connected to the same common line as a cell to be written in. The technique has already been proposed of applying an inhibit voltage to a source impurity region or drain impurity region of a non-selected memory transistor via a bit line or a source line at the time of writing or reading and thereby preventing erroneous writing and erroneous erasure of the non-selected memory transistor.
Also, in order to realize a NOR type one-transistor cell using a MONOS type memory transistor, it is necessary to sufficiently reduce the leakage current from memory transistors of non-selected cells in the erase state when controlling the threshold voltage. The leakage current may be reduced by just making the effective value of the threshold voltage higher seen from a well at the time of a read operation. From this viewpoint, the so-called source bias reading technique of supplying for example a positive voltage to the source line connected to the selected transistor has been proposed.
Summarizing the problems to be solved by the invention, when using the source bias reading technique in a NOR-type cell array, the threshold voltage of the memory transistor, based on the well potential, becomes higher regardless of whether the cell is a non-selected cell or selected cell. The rise of the threshold voltage has the advantage of reducing the leakage current for a non-selected cell.
At the same time, however, since the threshold voltage of the memory transistor of the selected cell also rises, there is the disadvantage that the read current from the selected cell falls when the reading gate voltage is constant.
The problem of the reduction of the read current is liable to become greater along with the increasing integration and miniaturization of memory cells.
If the number of cells connected to the same bit line increases as the memory cells become more highly integrated, the cumulative amount of the off-leakage currents from the non-selected cells increases. If the read current falls at this time, the noise margin of the read current abruptly falls and the possibility of erroneous operation rapidly rises.
Also, even if the number of cells connected to the same bit line is the same, when the gate length of the memory transistor is scaled for the purpose of making the cell smaller, the off-leakage current increases, so as similar situation arises.